About the Role

Senior ASIC Design Engineer role on the Cloud-Scale Machine Learning Acceleration team at AWS Annapurna Labs. Responsible for designing and optimizing hardware for AWS Machine Learning servers including AWS Inferentia. Focus on integrating subsystems into SoCs, implementing high-performance RTL, and analyzing design trade-offs.

Key Responsibilities

• Integrate multiple subsystems into top level SoC ensuring correct clock/reset/functional/DFT signal routing
• Implement and deliver high performance, area and power efficient RTL to achieve design targets
• Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements
• Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints
• Perform lint and clock domain crossing quality checks on the design

Required Skills & Qualifications

Must Have:

• Bachelor's degree in electrical engineering or equivalent
• 5+ years in RTL design for SoC
• 5+ years of VLSI engineering
• 5+ years with code quality tools including: Spyglass, LINT, or CDC

Nice to Have:

• Master's degree in electrical engineering, computer engineering, or equivalent
• Experience scripting for automation (e.g., Python, Perl, Ruby)
• Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints
• Familiarity with data path design, interconnects, AXI protocol
• Good analytical, problem solving, and communication skills

Benefits & Perks

• Work-life harmony with flexible working culture
• Inclusive team culture with employee-led affinity groups
• Mentorship and career growth opportunities
• Medical, financial, and other benefits
• Competitive compensation with geographic market adjustments