About the Role

Microsoft seeks a Design Verification Engineer for its AI System on Chip team to perform pre-silicon verification of complex IP and SoC designs. The role involves creating test plans, developing UVM environments, debugging failures, and collaborating across teams to deliver cutting-edge silicon.

Key Responsibilities

• Perform pre-silicon verification for complex IP, including creating test plans and UVM environments
• Write test cases, debug failures, run regression suites, and close coverage
• Interact with architects and design engineers to create verification strategies and test environments
• Develop verification components like scoreboards, sequences, constraints, and functional coverage
• Apply Agile development methodologies including code reviews and sprint planning

Required Skills & Qualifications

Must Have:

• Bachelor's, Master's, or Doctorate in Electronics Engineering, Computer Engineering, Computer Science, or related field with 4+ years technical engineering experience (or equivalent)
• 4+ years experience with Universal Verification Methodology (UVM), System Verilog, and Verification Fundamentals
• 2+ years debugging RTL (Verilog) designs and simulation/emulation environments
• 2+ years verification experience from definition to Silicon, including test plans, tests, debugging, and coverage signoff in C/C++ and UVM

Nice to Have:

• 5+ years design verification experience with UVM, System Verilog, and Verification Fundamentals
• Verification experience for IP or SoC related to CPUs, VPUs, GPUs, Tensor units, or similar
• Knowledge of System Verilog class, constraints, coverage, and assertions
• Hands-on experience in Formal property verification of computational data path designs

Benefits & Perks

• Industry leading healthcare