About the Role

ASIC Design Engineer responsible for designing and optimizing hardware for AWS machine learning servers, including AWS Inferentia. The role involves integrating subsystems into SoCs, implementing high-performance RTL, and working with cross-functional teams to deliver custom silicon solutions for cloud-scale machine learning acceleration.

Key Responsibilities

• Integrate multiple subsystems into top-level SoC, ensuring correct clock/reset/functional/DFT signal routing
• Implement and deliver high-performance, area and power efficient RTL to achieve design targets
• Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements
• Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints
• Perform lint and clock domain crossing quality checks on the design

Required Skills & Qualifications

Must Have:

• BS degree in electrical engineering or equivalent
• 5+ years in RTL design for SoC
• 5+ years in VLSI engineering
• 5+ years with code quality tools including: Spyglass, LINT, or CDC

Nice to Have:

• Master's degree in electrical engineering, computer engineering, or equivalent
• Experience scripting for automation (e.g., Python, Perl, Ruby)
• Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints
• Familiarity with data path design, interconnects, AXI protocol
• Good analytical, problem solving, and communication skills

Benefits & Perks

• Work-life harmony with flexible working culture
• Inclusive team culture with employee-led affinity groups
• Mentorship and career growth opportunities
• Medical, financial, and other benefits
• Competitive compensation with base pay ranging from $129,800 to $212,800/year